In the world of telecommunication, it is required to use more and more powerful processors in order to cope with the increasing amount of data to transmit and to receive. Therefore, the new processors to be devised have to provide two main characteristics of the data exchanges that are high speed and large capacity.
RISC processor is one of the most powerful processors. It can operate at high frequencies 33/66 MHz and with a 32-bit data bus. Therefore, RISC processors are expected to be a rapidly expanding branch of technology. By providing a Reduced Instructions Set Computer/Cycles, a highly effective computer system may be devised. They are used in today's network communication controller components for interfacing the system bus of the communication system. However, RISC processor uses a particular interface bus for allowing the communication between the processor and its peripherals, involving particular control signals and timing diagrams. Therefore, the direct connection of RISC processors to the peripherals which were currently designed for usual non RISC processors, also known as CISC processors is not directly possible, especially when the CISC bus complies with traditional INTEL bus structure and comprises a non-multiplexed data bus separated from the address bus, common control lines, control signals and timing diagrams which differ from the ones in RISC environment.
There is a desire to provide an interface circuit which allows the direct conversion between the signals existing on a RISC bus, and those exchanged by the usual CISC peripheral circuits. One of the solution often used in the state of the art is to implement a dual port RAM shared by a RISC processor, a 80.times.88 microprocessor and an internal communication protocol, refer to FIG. 1-A. In such an environment, the data are transferred from a network line (6) to a dual port RAM (9) under the control of both a network communication controller (7) and the 80.times.88 processor (11) on an 8-bit CISC bus (8) and then from the dual port RAM (9) to the memory adapter (14) under the control of a RISC processor (13) on a 32-bit RISC bus (12). This dual port RAM (9) requires the implementation of an arbiter (10) and a controller (10) which both degrade the performance. Consequently the high number of components required degrades the performance of the data transfer within the communication adapter.
The present invention is devised by taking into consideration the following remark: all the existing data network communication components using CISC bus interface can be reused in a RISC environment without any additional development, avoiding therefore to develop a new set of 32-bit communication components.